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8XC196NT CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE
Y Y Y Y Y Y Y Y Y Y Y Y
20 MHz Operation High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip OTPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Internal RAM Register-Register Architecture 4 Channel 10-Bit A D with Sample Hold 37 Prioritized Interrupt Sources Up to Seven 8-Bit (56) I O Ports Full Duplex Serial I O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port Selectable Bus Timing Modes for Flexible External Memory Interfacing
Reg RAM 1K
Y Y
Oscillator Fail Detection Circuitry High Speed Peripheral Transaction Server (PTS) Two Dedicated 16-Bit High-Speed Compare Registers 10 High Speed Capture Compare (EPA) Full Duplex Synchronous Serial I O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8- 16-Bit External Bus (Programmable) Programmable Bus (HOLD HLDA) 1 4 ms 16 x 16 Multiply 2 4 ms 32 16 Divide 68-Pin Package
Code RAM 512 Address Space 1 Mbyte IO 56 EPA 10 AD 4
Y
Y Y
Y Y Y
Y Y Y Y
Y
Device 8XC196NT
Pins Package 68P PLCC
OTPROM 32K
X e 7 OTPROM Device X e 0 ROMLESS
The 8XC196NT 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family The 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space 1000 bytes of register RAM 512 bytes of internal RAM 20 MHz operation and an optional 32 Kbytes of OTPROM Intel's CHMOS III-E process provides a high performance processor along with low power consumption Ten high-speed capture compare modules are provided As capture modules event times with 200 ns resolution can be recorded and generate interrupts As compare modules events such as toggling of a port pin starting an A D conversion pulse width modulation and software timers can be generated Events can be based on the timer or up down counter
December 1996
Order Number 272267-005
8XC196NT
272267 - 1
Figure 1 8XC196NT Block Diagram
PROCESS INFORMATION
This device is manufactured on P629 5 a CHMOS III-E process Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook Order Number 210997 Table 1 Thermal Characteristics Package Type PLCC iJA 36 5 C W iJC 13 C W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology
272267 - 2
EXAMPLE N87C196NT is 68-Lead PLCC OTPROM For complete package dimensional data refer to the Intel Packaging Handbook (Order Number 240800)
Figure 2 The 8XC186NT Familiy Nomenclature
2
8XC196NT
8XC196NT Memory Map Address (Note 7) FFFFFFH FFA000H FF9FFFH FF2080H FF207FH FF2000H FF1FFFH FF0600H FF05FFH FF0400H FF03FFH FF0100H FF00FFH FF0000H FEFFFFH 100000H FFFFFH 00A000H 009FFFH 002080H 00207FH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 000600H 0005FFH 000400H 0003FFH Register RAM 000100H 0000FFH 000018H 000017H 000000H Register RAM CPU SFR's External Memory Internal OTPROM or External Memory (Determined by EA Pin) RESET at FF2080H Reserved Memory (Internal OTPROM or External Memory) (Determined by EA Pin) External Memory Internal RAM (Identically Mapped into 00400H - 005FFH) External Memory Reserved for ICE External Memory for future devices 984 Kbytes External Memory Internal OTPROM or External Memory (Note 1) Reserved Memory (Internal OTPROM or External Memory) (Notes 1 3 and 6) Memory Mapped Special Function Registers (SFR's) Internal Special Function Registers (SFR's) (Note 5) External Memory Internal RAM (Address with Indirect or Indexed Modes) Upper Register File (Address with Indirect or Description
* *
Indexed Modes or through Windows ) (Note 2) Lower Register File (Address with Direct Indirect or Indexed Modes ) (Notes 2 4)
NOTES 1 These areas are mapped internal OTPROM if the REMAP bit (CCB2 2) is set and EA e 5V Otherwise they are external memory 2 Code executed in locations 00000H to 003FFH will be forced external 3 Reserved memory locations must contain 0FFH unless noted 4 Reserved SFR bit locations must be written with 0 5 Refer to 8XC196NT User's Guide and Quick Reference for SFR descriptions 6 WARNING The contents or functions of reserved memory locations may change with future revisions of the device Therefore a program that relies on one or more of these locations may not function properly 7 The 8XC196NT internally uses 24 bit address but only 20 address lines are bonded out allowing 1 Mbyte external address space
3
8XC196NT
272267 - 3
Figure 3 68-Pin PLCC Package Diagram
4
8XC196NT
PIN DESCRIPTIONS
Symbol VCC VSS VSS1 VSS1 VREF Main supply voltage ( a 5V) Digital circuit ground (0V) There are multiple VSS pins all of which MUST be connected Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Programming voltage for the OTPROM parts It should be a 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect to VCC if powerdown not being used Reference ground for the A D converter Must be held at nominally the same potential as VSS Input of the oscillator inverter and the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency is It has a 50% duty cycle Also LSIO pin the oscillator frequency Name and Function
VPP
ANGND XTAL1 XTAL2 P2 7 CLKOUT RESET P5 7 BUSWIDTH
Reset input to and open-drain output from the chip RESET has an internal pullup Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ``0'' and CCR1 bit 2 is ``1'' all bus cycles are 8-bit if CCR bit 1 is ``1'' and CCR1 bit 2 is ``0'' all bus cycles are 16-bit CCR bit 1 e ``0'' and CCR1 bit 2 e ``0'' is illegal Also an LSIO pin when not used as BUSWIDTH A positive transition causes a non maskable interrupt vector through memory location 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal OTPROM fetches INST is held low Also LSIO when not INST SLPCS is the Slave Port Chip Select Input for memory select (External Access) EA equal to a high causes memory accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip OTPROM EA equal to a low causes accesses to these locations to be directed to off-chip memory EA e a 12 5V causes execution to begin in the Programming Mode EA is latched at reset Bus Hold Input requesting control of the bus Bus Hold acknowledge output indicating release of the bus Bus Request output activated when the bus controller has a pending external memory cycle Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not used as ALE SLPADDR is the Slave Port Address Control Input and SLPALE is the Slave Port Address Latch Enable Input Read signal output to external memory RD is active only during external memory reads or LSIO when not used as RD SLPRD is the Slave Port Read Control Input
NMI P5 1 INST SLPCS
EA
HOLD HLDA BREQ P5 0 ALE ADV SLPADDR SLPALE
P5 3 RD SLPRD
5
8XC196NT
PIN DESCRIPTIONS (Continued)
Symbol P5 2 WR WRL SLPWR Name and Function Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is active during external memory writes Also an LSIO pin when not used as WR WRL SLPWR is the Slave Port Write Control Input Byte High Enable or Write High output as selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects that bank of memory that is connected to the low byte Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is only valid during 16-bit external memory read write cycles Also an LSIO pin when not BHE WRH Ready input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The max number of wait states inserted into the bus cycle is controlled by the CCR CCR1 Also an LSIO pin when READY is not selected Dual function I O pin As a bidirectional port pin or as a system function The system function is a Slave Port Interrupt Output Pin Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Clock input The TIMER1 will increment or decrement on both positive and negative edges of this pin Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Direction input The TIMER1 will increment when this pin is high and decrements when this pin is low Dual function I O port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare EPA0 and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer counter 4-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins are also used as inputs to OTPROM parts to select the Programming Mode Dual function I O ports that have a system function as Synchronous Serial I O Two pins are clocks and two pins are data providing full duplex capability 8-bit multi-functional port All of its pins are shared with other functions 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups 8-bit bidirectional standard and I O port These bits are shared with the extended address bus A16 - A19 Pin function is selected on a per pin basis Interrupt Output This active-low output indicates that a pending interrupt requires use of the external bus Slave Port Address Data Bus
P5 5 BHE WRH
P5 6 READY
P5 4 SLPINT P6 2 T1CLK
P6 3 T1DIR
PORT1 EPA0-7 P6 0-6 1 EPA8-9 PORT 0 ACH4-7
P6 3-6 7 SSIO PORT 2 PORT 3 and 4 EPORT INTOUT SLP0-SLP7
6
8XC196NT
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Voltage from VPP or EA to VSS or ANGND
b 60 C to a 150 C b 0 5V to a 13 0V
Voltage from Any Other Pin b 0 5 to a 7 0V to VSS or ANGND This includes VPP on ROM and CPU devices Power Dissipation 0 5W
NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
OPERATING CONDITIONS
Symbol TA VCC VREF FOSC Parameter Ambient Temperature Under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min 0 4 50 4 50 4 Max
a 70
Units C V V MHz (Note 4)
5 50 5 50 20
NOTE ANGND and VSS should be nominally at the same potential
DC CHARACTERISTICS
Symbol ICC IREF IIDLE IPD VIL VIH VIH1 VIH2 VOL Parameter VCC Supply Current
(Under Listed Operating Conditions)
Min Typ Max 90 5 40 50
b 0 5V
Units mA mA mA mA V V V V V V V V V V
Test Conditions XTAL1 e 20 MHz VCC e VPP e VREF e 5 5V (While device in Reset) XTAL1 e 20 MHz VCC e VPP e VREF e 5 5V VCC e VPP e VREF e 5 5V(11) For PORT0(10) For PORT0(10) XTAL1 Input Pin Only(1) RESET input pin only IOL e 200 mA(3 5) IOL e 3 2 mA IOL e 7 0 mA IOH e b 200mA(3 5) IOH e b 3 2 mA IOH e b 7 0 mA VSS k VIN k VCC VCC k VIN k VREF VIN e 0 45V(1)
A D Reference Supply Current Idle Mode Current Powerdown Mode Current(6) Input Low Voltage (all pins) Input High Voltage Input High Voltage XTAL1 Input High Voltage on RESET Output Low Voltage (Outputs Configured as Complementary) Output High Voltage (Outputs Configured as Complementary) Input Leakage Current (Std Inputs) Input Leakage Current (Port 0) Logical 0 Input Current VCC b 0 3 VCC b 0 7 VCC b 1 5
75 0 3 VCC VCC a 0 5 VCC a 0 5 VCC a 0 5 03 0 45 15
0 7 VCC 0 7 VCC 0 7 VCC
VOH
ILI ILI1 IIL
g10 g3
mA mA mA
b 70
7
8XC196NT
DC CHARACTERISTICS
Symbol VOL1 VOH1 VOH2 CS RWPU RRST
(Under Listed Operating Conditions) (Continued)
Min Typ Max 08 20 VCC b 1V 10 150K 65K 180K Units V V V pF X X Test Conditions (Note 7) IOH e 0 8 mA(7) IOH e b 6 mA(1) ftest e 1 0 MHz (Note 6)
Parameter Output Low Voltage in RESET SLPINT (P5 4) and HLDA (P2 6) Output High Voltage in RESET Output High Voltage in RESET Pin Capacitance (Any pin to VSS) Weak Pullup Resistance Reset Pullup
NOTES 1 All BD (bidirectional) pins except INST and CLKOUT INST and CLKOUT are excluded due to their not being weakly pulled high in reset BD pins include Port1 Port2 Port3 Port4 Port5 Port6 and EPORT except SPLINT (P5 4) and HLDA (P2 6) 2 Standard input pins include XTAL1 EA RESET and Port 1 2 5 6 and EPORT when setup as inputs 3 All bidirectional I O pins when configured as Outputs (Push Pull) 4 Device is static and should operate below 1 Hz but only tested down to 4 MHz 5 Maximum IDL IDH currents per pin are as follows a ) Test Condition VOH e VCC b 0 7V Part 1 Part 2 Part 3 Part 4 Part 5 Part 6 IOL IOL IOL IOL IOL IOL
e e e e e e
VOL e 0 45V
0 65 mA 8 0 mA 7 5 mA 7 5 mA 9 0 mA 8 0 mA
IOH IOH IOH IOH IOH IOH
e e e e e e
7 5 mA 12 0 mA 7 5 mA 7 5 mA 9 0 mA 9 0 mA VOL e 1 5V
b ) Test Condition VOH e VCC b 1 5V
e e e e e e e e e e e e
21 0 mA IOH 26 0 mA Part 1 IOL 26 0 mA IOH 29 0 mA Part 2 IOL 17 0 mA IOH 25 0 mA Part 3 IOL 16 0 mA IOH 25 0 mA Part 4 IOL 21 0 mA IOH 28 0 mA Part 5 IOL 19 0 mA IOH 26 0 mA Part 6 IOL 6 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and VREF e VCC e 5 5V 7 Violating these specifications in reset may cause the device to enter test modes (P5 4 and P2 6) 8 TBD e To Be Determined 9 Pullup present during return from powerdown condition 10 When P0 is used as analog inputs refer to A D specifications 11 For temperatures k100 C typical is 10 mA
272267 - 24
8
8XC196NT
8XC196NT ADDITIONAL BUS TIMING MODES
The 8XC196NT device has 3 additional bus timing modes for external memory interfacing MODE 3 Mode 3 is the standard timing mode Use this mode for systems that emulate the 8XC196KR bus timings MODE 0 Mode 0 is the standard timing mode but 1 (minimum) wait state is always inserted in external bus cycles MODE 1 Mode 1 is the long R W mode This mode advances RD and WR signals by 1 TOSC creating a 2 TOSC RD WR low time ALE is also advanced by 0 5 TOSC but ALE high time remains 1 TOSC MODE 2 Mode 2 is the long R W mode with Early Address Mode 2 is similar to Mode 1 with respect to RD WR and ALE signals Additionally the address is output on the bus 0 5 TOSC earlier in the bus cycle
272267 - 4
Figure 4 Detailed MODE 1 2 3 Comparison
9
8XC196NT
EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ``T'' for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points
Conditions H High L Low V Valid X No Longer Valid Z Floating
Signals A Address B BHE BR BREQ C CLKOUT D DATA G Buswidth H HOLD
HA HLDA L ALE ADV Q Data Out RD RD W WR WRH WRI X XTAL1 Y READY
BUS MODE 0 and 3 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The system must meet these specifications to work with the 8XC196NT Symbol TAVYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX Parameter Address Valid to Ready Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 0 3 TOSC b 55 TOSC b 30 TOSC b 60 TOSC 0 Min Max 2 TOSC b 75 No Upper Limit TOSC b 30 2 TOSC b 75 TOSC b 60 Units ns(3) ns ns(1) ns(2 3) ns(2 3) ns ns(2) ns(2) ns ns ns
NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC c n where n e number of wait states 3 If mode 0 is selected one wait state minimum is always added If additional wait states are required add 2 TOSC to the specification
10
8XC196NT
BUS MODE 0 and 3 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 8XC196NT will meet these specifications Symbol FXTAL TOSC TXHCH TOFD TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low Clock Failure to Reset Pulled Low(6) CLKOUT Period CLKOUT High Period CLKOUT Low to ALE ADV High ALE ADV Low to CLKOUT High ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period Data Hold after WR High WR High to ALE ADV High BHE INST Hold after WR High AD8-15 Hold after WR High BHE INST Hold after RD High AD8-15 Hold after RD High TOSC b 10
b 10 a 25
Min 40 50
a 20
Max 20 250 110 40 2 TOSC
Units MHz(1) ns ns ms ns ns ns ns ns(5) ns ns ns ns
4
TOSC b 10
b 10 b 25
TOSC a 30
a 15 a 15
4 TOSC TOSC b 10 TOSC b 15 TOSC b 40 TOSC b 40
b5 a 35
TOSC a 10
ns ns(5) ns(3) ns ns ns ns
TOSC b 5 TOSC TOSC a 25
a5
TOSC b 23
b 10 a 15
ns ns(5) ns ns(3) ns ns(4) ns ns(4)
TOSC b 30 TOSC b 35 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 10 TOSC b 30 TOSC a 15
NOTES 1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 TOSC c n where n e number of wait states If mode 0 (1 automatic wait state added) operation is selected add 2 TOSC to specification 6 TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H NT NQ customer QROM codes need to equate location 2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired Intel manufacturing uses location 2016H as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit Programming the CDE bit enables oscillator fail detection
11
8XC196NT
BUS MODE 0 and 3
8XC196NT SYSTEM BUS TIMING
272267 - 5
If mode 0 operation is selected add 2 TOSC to this time
12
8XC196NT
8XC196NT MODE 0 and 3
READY TIMINGS (ONE WAIT STATE)
272267 - 6
If mode 0 selected one wait state is always added If additional wait states are required add 2 TOSC to these specifications
MODE 0 and 3
8XC196NT BUSWIDTH TIMINGS
272267 - 7
If mode 0 selected add 2 TOSC to these specifications
13
8XC196NT
BUS MODE 1 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The system must meet these specifications to work with the 8XC196NT Symbol TAVYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX Parameter Address Valid to Ready Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 0 3 TOSC b 60 2 TOSC b 44 TOSC b 60 TOSC 0 Min Max 2 TOSC b 75 No Upper Limit TOSC b 30 2 TOSC b 75 1 5 TOSC b 60 Units ns ns ns(1) ns ns ns ns(2) ns(2) ns ns ns
NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC c n where n e number of wait states
14
8XC196NT
BUS MODE 1 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 8XC196NT will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCHLH TCLLL TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHIX TWHAX TRHBX TRHIX TRHAX Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low CLKOUT Period CLKOUT High Period CLKOUT HIGH to ALE ADV High CLKOUT LOW to ALE ADV Low ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period Data Hold after WR High WR High to ALE ADV High BHE Hold after WR High INST Hold after WR High AD8-15 Hold after WR High BHE Hold after RD High INST Hold after RD High AD8-15 Hold after RD High 0 5 TOSC b 10 TOSC b 15 2 TOSC b 23 b 10 2 TOSC b 15 0 5 TOSC b 12 0 5 TOSC b 10 TOSC b 15 0 5 TOSC b 15 0 5 TOSC b 30 TOSC b 32 0 5 TOSC b 32 0 5 TOSC b 30 ns(4) ns ns(4) 0 5 TOSC a 15 TOSC a 25
a 15
Min 80 50
a 20
Max 20 125 110 2 TOSC TOSC a 27 0 5 TOSC a 15 0 5 TOSC a 15 TOSC a 10
Units MHz(1) ns ns ns ns ns ns ns(5) ns ns ns ns
TOSC b 10 0 5 TOSC b 15 0 5 TOSC b 25 TOSC b 20 0 5 TOSC b 20 0 5 TOSC b 25 0 5 TOSC b 15 TOSC b 10 2 TOSC b 20 0 5 TOSC
4 TOSC
TOSC a 30 0 5 TOSC a 25
a5
ns ns(5) ns(3) ns ns ns ns ns ns(5) ns ns(3) ns
NOTES 1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 TOSC c n where n e number of wait states
15
8XC196NT
MODE 1
8XC196NT SYSTEM BUS TIMING
272267 - 8
16
8XC196NT
MODE 1
8XC196NT READY TIMINGS (ONE WAIT STATE)
272267 - 9
MODE 1
8XC196NT BUSWIDTH TIMINGS
272267 - 10
17
8XC196NT
BUS MODE 2 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The system must meet these specifications to work with the 8XC196NT Symbol TAVYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX Parameter Address Valid to Ready Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 0 3 5 TOSC b 55 2 TOSC b 44 TOSC b 60 0 5 TOSC 0 Min Max 2 5 TOSC b 75 No Upper Limit TOSC b 30 2 5 TOSC b 75 1 5 TOSC b 60 Units ns ns ns(1) ns ns ns ns(2) ns(2) ns ns ns
NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC c n where n e number of wait states
18
8XC196NT
BUS MODE 2 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 8XC196NT will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCHLH TCLLL TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHIX TWHAX TRHBX TRHIX TRHAX Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low CLKOUT Period CLKOUT High Period CLKOUT HIGH to ALE ADV High CLKOUT LOW to ALE ADV Low ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period Data Hold after WR High WR High to ALE ADV High BHE Hold after WR High INST Hold after WR High AD8-15 Hold after WR High BHE Hold after RD High INST Hold after RD High AD8-15 Hold after RD High 0 5 TOSC b 10 TOSC b 22 2 TOSC b 25
b 10 a 15
Min 80 50
a 20
Max 20 125
a 85
Units MHz(1) ns ns ns
2 TOSC TOSC b 10 0 5 TOSC b 15 0 5 TOSC b 25 TOSC b 20 TOSC b 15 0 5 TOSC b 20 0 5 TOSC b 15 TOSC b 10 2 TOSC b 20 0 5 TOSC b 5 0 5 TOSC a 25
a5
TOSC a 27 0 5 TOSC a 15 0 5 TOSC a 15 TOSC a 10
ns ns ns ns(5) ns ns ns ns
4 TOSC
TOSC a 30
ns ns(5) ns(3) ns ns
TOSC a 25
ns ns ns ns(5) ns ns(3) ns ns(4) ns ns(4)
2 TOSC b 20 0 5 TOSC b 12 0 5 TOSC b 10 TOSC b 15 0 5 TOSC b 15 0 5 TOSC b 30 TOSC b 32 0 5 TOSC b 32 0 5 TOSC b 30 0 5 TOSC a 10
NOTES 1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 TOSC c n where n e number of wait states
19
8XC196NT
MODE 2
8XC196NT SYSTEM BUS TIMING
272267 - 11
20
8XC196NT
MODE 2
8XC196NT READY TIMINGS (ONE WAIT STATE)
272267 - 12
MODE 2
8XC196NT BUSWIDTH TIMINGS
272267 - 13
21
8XC196NT
BUS MODE 0 1 2 and 3 HOLD HLDA TIMINGS (Over Specified Operation Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV HOLD Setup Time CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid
b 25 b 25 b 15 b 10
Parameter
Min
a 65 b 15 b 15
Max
Units ns(1)
a 15 a 15 a 25 a 25 a 15 a 25
ns ns ns ns ns ns ns ns
NOTE 1 To guarantee recognition at next clock
8XC196NT HOLD HLDA TIMINGS
272267 - 14
22
8XC196NT
AC CHARACTERISTICS
SLAVE PORT WAVEFORM
SLAVE PORT
(SLPL e 0)
272267 - 15
SLAVE PORT TIMING Symbol TSAVWL TSRHAV TSRLRH TSWLWH TSRLDV TSDVWH TSWHQX TSRHDZ
(SLPL e 0) Parameter Address Valid to WR Low RD High to Address Valid RD Low Period WR Low Period RD Low to Output Data Valid Input Data Setup to WR High WR High to Data Invalid RD High to Data Float 20 30 15 Min 50 60 TOSC TOSC 60 Max Units ns ns ns ns ns ns ns ns
NOTES 1 Test Conditions FOSC e 20 MHz TOSC e 50 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change
23
8XC196NT
AC CHARACTERISTICS
SLAVE PORT WAVEFORM
SLAVE PORT (Continued)
(SLPL e 1)
272267 - 16
SLAVE PORT TIMING Symbol TSELLL TSRHEH TSLLRL TSRLRH TSWLWH TSAVLL TSLLAX TSRLDV TSDVWH TSWHQX TSRHDZ
(SLPL e 1) Parameter CS Low to ALE Low RD or WR High to CS High ALE Low to RD Low RD Low Period WR Low Period Address Valid to ALE Low ALE Low to Address Invalid RD Low to Output Data Valid Input Data Setup to WR High WR High to Data Invalid RD High to Data Float 20 30 15 Min 20 60 TOSC TOSC TOSC 20 20 60 Max Units ns ns ns ns ns ns ns ns ns ns ns
NOTES 1 Test Conditions FOSC e 20 MHz TOSC e 50 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change
24
8XC196NT
EXTERNAL CLOCK DRIVE
Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 4 50 0 35 c TOSC 0 35 c TOSC Max 20 250 0 65 TOSC 0 65 TOSC 10 10 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272267 - 17
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272267 - 19 272267 - 18
AC Testing inputs are driven at 3 5V for a logic ``1'' and 0 45V for a logic ``0'' Timing measurements are made at 2 0V for a logic ``1'' and 0 8V for logic ``0''
For timing purposes a Port Pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH VOL level occurs IOL IOH s 15 mA
25
8XC196NT
WAVEFORM
SERIAL PORT
SHIFT REGISTER MODE
SERIAL PORT WAVEFORM
SHIFT REGISTER MODE (MODE 0)
272267 - 20
AC CHARACTERISTICS
SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING SHIFT REGISTER MODE (MODE 0) Test Conditions TA e b 40 C to a 125 C VCC e 5 0V g10% VSS e 0 0V Load Capacitance e pF Symbol TXLXL(2) TXLXL(2) TQVXH TXHQX TXHQV TDVXH Parameter Serial Port Clock Period (BRR t 8002H) Receive Only Min 6 TOSC 4 TOSC 3 TOSC 2 TOSC b 50 2 TOSC a 50 2 TOSC a 200 0 5 TOSC Max Units ns ns ns ns ns ns ns ns ns ns
TXLXH(2) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) 4 TOSC b 50 4 TOSC a 50 Serial Port Clock Period (BRR e 8001H) Transmit Only TXLXH(2) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC b 50 2 TOSC a 50 Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge
TXHDX(1) Input Data Hold after Clock Rising Edge TXHQZ(1) Last Clock Rising to Output Float
NOTES 1 Parameters not tested 2 The minimum baud rate register value for Receive is 8002H The minimum baud rate register value for Transmit is 8001H
26
8XC196NT
A to D CHARACTERISTICS
The A D converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF
10-BIT MODE A D OPERATING CONDITIONS
Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min 0 4 50 4 50 10 10 40 15 20 Max
a 70
Units C V V(1) ms(2) ms(2) MHz
5 50 5 50
NOTES 1 VREF must be within 0 5V of VCC 2 The value of AD TIME is selected to meet these specifications
10-BIT MODE A D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 30
An ``LSB'' as used here has a value of approximately 5 mV
g1 0 g0 1 g0 25
(Using Above Operating Conditions)(6) Min 1024 10 0 Max 1024 10
g3 0
Typ (1)
Units Level Bits LSBs LSBs LSBs
0 25 g0 5 0 25 g0 5 1 0 g2 0
b 0 75
g3 0
LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1)
a 0 75
g1 0
0 0
0 009 0 009 0 009
b 60 b 60 b 60
dB(1 2 3) dB(1 2) dB(1 2)
750 0 ANGND b 0 5
1 2K
g3 0
X(4) mA V(5) pF
VREF a 0 5
NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break-before-make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted 6 All conversions performed with processor in IDLE mode
27
8XC196NT
8-BIT MODE A D OPERATING CONDITIONS
Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min 0 4 50 4 50 10 7 40 20 20 Max
a 70
Units C V V(1) ms(2) ms(2) MHz
5 50 5 50
NOTES 1 VREF must be within 0 5V of VCC 2 The value of AD TIME is selected to meet these specifications
8-BIT MODE A D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 30
g1 0 g0 25 g0 5 g0 5
(Using Above Operating Conditions)(6) Min 256 8 0 Max 256 8
g1 0
Typ (1)
Units Level Bits LSBs LSBs LSBs
0
b0 5
g1 0
LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1)
a0 5
g1 0
0 0
0 003 0 003 0 003
b 60 b 60 b 60
dB(1 2 3) dB(1 2) dB(1 2) X(4) mA V(5) pF
750 0 ANGND b 0 5
1 2K
g3 0
VREF a 0 5
An ``LSB'' as used here has a value of approximately 5 mV NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break-before-make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 Applying voltage beyond these specifications will degrade the accuracy of other channels being converted 6 All conversions performed with processor in IDLE mode
28
8XC196NT
OTPROM SPECIFICATIONS
OPERATING CONDITIONS Symbol TA VCC VREF VPP VEA FOSC FOSC Description Ambient Temperature During Programming Supply Voltage During Programming Reference Supply Voltage During Programming Programming Voltage EA Pin Voltage Oscillator Frequency during Auto and Slave Mode Programming Oscillator Frequency during Run-Time Programming Min 20 45 45 12 25 12 25 60 60 Max 30 55 55 12 75 12 75 80 20 0 Units C V(1) V(1) V(2) V(2) MHz MHz
NOTES 1 VCC and VREF should nominally be at the same voltage during programming 2 VPP and VEA must never exceed the maximum specification or the device may be damaged 3 VSS and ANGND should nominally be at the same potential (0V) 4 Load capacitance during Auto and Slave Mode programming e 150 pF
AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH TLHPL TPHLL TPHDX TPHPL TLHPL TPLDV TSHLL TPHIL TILIH TILVH TILPL TPHVL Parameter Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE Pulse Width PROG Pulse Width(2) PALE High to PROG Low PROG High to next PALE Low Word Dump Hold Time PROG High to next PROG Low PALE High to PROG Low PROG Low to Word Dump Valid RESET High to First PALE Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 1100 0 240 50 170 220 220 220 50 Min 0 100 0 400 50 50 220 220 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
NOTES 1 Run-time programming is done with FOSC e 6 0 MHz to 10 0 MHz VCC VPD VREF e 5V g0 5V TC e 25 C g5 C and VPP e 12 5V g0 25V For run-time programming over a full operating range contact factory 2 This specification is for the word dump mode For programming pulses use Modified Quick Pulse Algorithm
29
8XC196NT
DC OTPROM PROGRAMMING CHARACTERISTICS Symbol IPP Parameter VPP Programming Supply Current Min Max 200 Units mA
NOTE Do not apply VPP unti VCC is stable and within specifications and the oscillator clock has stabilized or the device may be damaged
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
272267 - 21
NOTE P3 0 must be high (``1'')
SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT
272267 - 22
NOTE P3 0 must be low (``0'')
30
8XC196NT
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT
272267 - 23
This data sheet (272267-004) applies to devices marked with a ``D'' at the end of the top side tracking number
The following are differences between the 272267003 and 272267-004 datasheets 1 Changed all references of ``EPROM'' to ``OTPROM'' 2 3 4 5 6 7 Added all the Slave Port pins to the package diagram and pin descriptions Added INTOUT pin to pin descriptions Changed ILI1 (input leakage current for Port 0) from g1 mA to g3 mA Removed TLLYV from AC characterisics and waveform diagrams TRLCL in Mode 0 and 3 changed from a 4 ns min to b 5 ns min TWHQX in Mode 0 and 3 changed from TOSC b 30 min to TOSC b 35 min Clarified the Ready waveform timings for Mode 0 and 3 by adding `` a 2 TOSC '' TLHLL in Mode 1 changed from TOSC b 10 min to TOSC b 20 min TAVLL in Mode 1 changed from 0 5 TOSC b 15 min to 0 5 TOSC b 20 min TLLAX in Mode 1 changed from 0 5 TOSC b 20 min to 0 5 TOSC b 25 min TLHLL in Mode 2 changed from TOSC b 10 min to TOSC b 20 min TXLXL and TXLXH for the Serial Port timings were changed to reflect the minimum baudrate for receive and transmit modes Added the 8XC196NT ERRATA section 31
8XC196NT Design Considerations
1 When operating in bus timing modes 1 or 2 the upper and lower address data lines must be latched Even in 8-bit bus mode the upper address lines must be latched In modes 0 and 3 the upper address lines DO NOT NEED to be latched in 8-bit bus width mode But in 16-bit buswidth mode the upper address lines need to be latched
8XC196NT ERRATA see Faxback 2344
1 ILLEGAL Opcode interrupt vector 2 Aborted Interrupt vectors to lowest priority 3 PTS Request during Interrupt latency
8 9 10
DATA SHEET REVISION HISTORY
This datasheet applies to devices marked with a ``D'' at the end of the topside tracking number The topside tracking number consists of nine characters and is the second line on the top side of the device Datasheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices
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